PWR_DOWN_CTRL_I=Val_0x0, PWR_CLAMP_CTRL_I=Val_0x0, PWR_ISOLATE_I=Val_0x0, RMII_CLKSEL=Val_0x0
ETH Control Register
| PWR_DOWN_CTRL_I | ETH power down control 0 (Val_0x0): Power ON. The whole ETH module is powered-ON. 1 (Val_0x1): Power OFF. All ETH blocks are powered-OFF except the always-ON logic. |
| PWR_ISOLATE_I | Isolation cells enable The isolation cells isolate the signals of the ETH powered-OFF domain from the always-ON domain. 0 (Val_0x0): Isolation cells disabled 1 (Val_0x1): Isolation cells enabled and provide required signal values to the ETH always-ON domain |
| PWR_CLAMP_CTRL_I | ETH always-ON logic reset control 0 (Val_0x0): ETH always-ON logic is not in reset (resets are inactive) 1 (Val_0x1): ETH always-ON logic is in reset (resets are active) |
| SBD_FLOWCTRL_I | ETH sideband flow control When set to 0x1, instructs the MAC to transmit Pause frames in full-duplex mode. In half-duplex mode, the MAC enables the backpressure function until this bit is set to 0x0. |
| RMII_CLKSEL | Select RMII clock source 0 (Val_0x0): RMII clock source from ETH_REFCLK pin 1 (Val_0x1): RMII clock source from internal 50 MHz PLL clock |